Integrated electronic semiconductor devices often have to cope with capacitive loads that have to be charged and discharged to certain voltage levels. There are stages with an input capacitance, as for example comparators, buffers or amplifiers that are switched on and off, as well as simple capacitances or cables.
If the drain current of a MOS transistor changes its gate-source voltage must change, too and therefore the gate charge must change. If an amplifier with a MOS input transistor is switched on or off (i.e. the bias current is switched on or off) this charge will be seen as kick-back noise at the input.
The input nodes of these stages are often connected to high impedance voltage reference sources. The input capacitances at the input nodes of these stages will then receive or release a certain amount of charge that may propagate from their input nodes, i.e. their input capacitances, to or from the high impedance voltage reference sources. The released or supplied charge can cause a voltage drop across the interconnections (wires, VIAs etc.) or at the voltage sources i.e. their output impedances. The voltage level at the input node may then vary. If this voltage level is monitored, for example by a comparator which may also be coupled to the input node, this can cause the comparator to change the state of its output signal.
FIG. 1 shows a simplified circuit diagram of an example of a first stage ST1 having an input capacitance. FIG. 1 illustrates the effect of kickback noise. There is a switched electronic stage ST1, which may be an amplifier or a comparator or any other device stage having an input capacitance (also a simple switched capacitor etc.). The first stage ST1 may comprise an input stage with a differential pair of transistors, as for example, transistors M1 and M2. The input stage may further be coupled to a current source CS for feeding a tail current to the input stage. In order to save power or for any other reasons, the input stage M1, M2 may be switched off by disconnecting the input stage from the current source CS by switch SW.
The node N1 connects the gate of one of the input transistors M1 to a voltage source VS. This voltage source VS may be a voltage source having a comparatively high output impedance RI. It may be modeled with a reference voltage source VREF and an output impedance RI as shown in FIG. 1. There might be a second stage ST2 having an input that is sensitive to charge injection and/or voltage glitches. The second stage ST2 may be comparator. A comparator may be coupled with an inverting input to the node N1. The positive input of the comparator may receive another reference voltage VM. The output signal COMPOUT of comparator may then be used as an indicator as to whether the voltage level at node N1 is greater or lower the reference voltage level VM. The input MOSFET M1 (as all MOS transistors) of the first stage ST1 has the input capacitances CGD (gate to drain capacitance) and CGS (gate to source capacitance). If the switch SW is turned off (disconnected) the input capacitance (CGD, CGS) of the input node INN releases a charge QK that can propagate towards voltage source VS causing a voltage drop at resistor RI. The same effect in reverse can occur, when the first stage is activated by switch SW. The charge may then propagate towards the input capacitances of the first stage ST1. This may decrease or increase the voltage level at node N1, thereby varying the voltage at the inverting input of the comparator. In response to this, the output COMPOUT of the comparator may change.
FIG. 2 shows a simplified circuit diagram of a configuration which is basically similar to the one shown in FIG. 1. However, the circuit shown in FIG. 2 further includes a high performance buffer BUF for buffering the reference voltage provided by the voltage source VS. The kickback noise or kickback charge QK propagating from the input node ST1IN towards voltage reference source VS is then blocked by high performance buffer BUF. However, even in this situation, the voltage level at node N1 may vary. Therefore, the comparator ST2 is coupled between the positive input of high performance buffer BUF and voltage source VS. However, a main disadvantage of the configuration shown in FIG. 2 is the power consumption of the high performance buffer. The buffer BUF constantly consumes supply current and may also add an offset voltage.